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Silicon Labs /Series1 /EFM32PG1B /EFM32PG1B100F128IM32 /CMU /AUXHFRCOCTRL

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Interpret as AUXHFRCOCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TUNING0FINETUNING0FREQRANGE0CMPBIAS 0 (LDOHP)LDOHP 0 (DIV1)CLKDIV 0 (FINETUNINGEN)FINETUNINGEN 0VREFTC

CLKDIV=DIV1

Description

AUXHFRCO Control Register

Fields

TUNING

AUXHFRCO Tuning Value
FINETUNING

AUXHFRCO Fine Tuning Value
FREQRANGE

AUXHFRCO Frequency Range
CMPBIAS

AUXHFRCO Comparator Bias Current
LDOHP

AUXHFRCO LDO High Power Mode
CLKDIV

Locally Divide AUXHFRCO Clock Output

0 (DIV1): Divide by 1.

1 (DIV2): Divide by 2.

2 (DIV4): Divide by 4.
FINETUNINGEN

Enable Reference for Fine Tuning
VREFTC

AUXHFRCO Temperature Coefficient Trim on Comparator Reference

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data